Notice: The current evaluation report is intended solely for the purpose of soliciting comments. The team kindly requests your valuable feedback and suggestions. We are committed to continuously revising the report based on the available evidence.

Background

The evolution of chip technology indeed represents a remarkable trajectory, originating from the advent of computers in the 1940s. The revolutionary concept of integrated circuits, which significantly transformed the field, can be traced back to the genesis of Boolean algebra in 1854. This innovative idea of symbolizing logical operations via binary digits established the cornerstone for contemporary digital circuits. Over subsequent decades, the progression of chip development has burgeoned into an extensive industry and ecosystem. The advancements in semiconductor manufacturing technology have facilitated the production of progressively miniaturized yet more potent chips, with transistor dimensions now quantified in nanometers. This incessant trend towards miniaturization has catalyzed an exponential augmentation in computing power, fostering breakthroughs in diverse domains such as artificial intelligence, mobile technology, and the Internet of Things.

Evaluation Standards

We single out the latest Chip achievements from 2022 to 2023 which already have growing impacts or would have impacts in the near future. Our evaluation criteria are as follows:

  • The original or pioneering works in chips.
  • The works that play a significant role in promoting the development of chips.
  • The works that would have impacts in the near future disscused by the committee, for example, publishing high quality papers and being gained attention.

Chip100: Top 100 Chips achievements （2022-2023）

Overview of Top Chips achievements

（Please note that the tree diagram can be zoomed in, zoomed out, and moved. You can click on the circles at the branches to expand or collapse the content of the diagram.）

Top Chips Achievements

When considering the main academic contributors, we only list:

  • the first author (including the authors with equal contribution)
  • the corresponding author (the last author if there is no corresponding author)

If you have any comments or suggestions about the list, please send an email to benchcouncil.evaluation@gmail.com

Categories Sub-Categories Work Main Contributors Institution Country
Chips Design System-level Design PhotoFourier Deep Neural Network Accelerator Shurui Li, Puneet Gupta UCLA USA
INCA Deep Neural Network Accelerator Bokyung Kim,Hai Li Duke University USA
Admission-Controlled Instruction Cache Yunjin Wang, Niranjan Soundararajan The Pennsylvania State University,Intel Labs USA,India
Vision Transformers Accelerator Haoran You, Yingyan Lin Georgia Institute of Technology USA
The Manycore-FPGA Architecture Ang Li, David Wentzlaff Princeton USA
Virtualizing Virtual Channel Hans Kasan, John Kim KAIST Korea
The dataflow architecture for GNN acceleration Rishov Sarkar, Cong Hao Georgia Institute of Technology USA
CARE Cache Management Xiaoyang Lu, Xian-He Sun Illinois Institute of Technology USA
VAQUERO Vector Accelerator Julian Pavon, Adrian Cristal Barcelona Supercomputing Center,Universitat Politecnica de Catalunya Spain
TaskFusion Transfer Learning Architecture Zichen Fan, Dennis Sylvester University of Michigan USA
Microarchitecture/circuit co-design Dibei Chen,Leibo Liu Tsinghua University China
Machine Learning Assisted Architecture Design Srivatsan Krishnan,Vijay Janapa Reddi Harvard University USA
SDSoW Jiangxing Wu NDSC China
C-Ecosystem for Chips Ninghui Sun ICT China
LoongArch weiwu Hw Loongson,ict China
SPADE Matrix Multiplication Accelerator Gerasimos Gerogiannis, Josep Torrellas UIUC USA
NeuRex Neural Rendering Acceleration Junseo Lee, Jaewoong Sim Seoul National University Korea
RAELLA Processing-In-Memory Tanner Andrulis, Vivienne Sze MIT USA
AMG Multi-modal computing unit Xiaofeng Hou, Chao Li, Kwang-Ting Cheng ACCESS, Shanghai Jiao Tong University China
TPUv4 Norman P. Jouppi, David Patterson Google USA
RSQP General-purpose Quadratic Program Solver Maolin Wang, Hayden Kwok-Hay So AI Chip Center for Emerging Smart Systems, University of Hong Kong China
Neural graphics Acceleration Muhammad Husnain Mubarik, Rakesh Kumar UIUC USA
ECSSD Co-designed in-storage-computing architecture Siqi Li, Yuan Xie UCSB, DAMO Academy China.USA
Sharing-Aware Caching in GPU Shiqing Zhang, Lieven Eeckhout Ghent University Belgium
FPGA-based full-stack TCP acceleration framework Junehyuk Boo, Jangwoo Kim Seoul National University, MangoBoost Inc Korea
HGNNs accelerator Dan Chen, Long Zheng Huazhong University of Science and Technology China
Cost-aware Cache Replacement Nayana Prasad Nagendra, Bhargav Reddy Godala, David I. August Princeton University USA
Decoupled Vector Runahead Ajeya Naithani, Lieven Eeckhout Ghent University Belgium
CryptoMMU Faiz Alam, Amro Awad North Carolina State University USA
Branch Target Buffer Organizations Arthur Perais， Rami Sheikh CNRS, ARM UK,France
Warming Up a Cold Front-End withIgnite David Schall, Boris Grot University of Edinburgh UK
MicroarchitectureExploration Via Bottleneck Analysis Chen Bai, Yuan Xie The Chinese University of HongKong, Alibaba China
Efficient Unified GPU Memory and Storage Architecture Haoyang Zhang, Jian Huang UIUC USA
Compute Fabric Switch Chip Lixin Zhang Sudo Information Technology China
Fault-Tolerant Quantum Computing Suhas Vittal, Moinuddin Qureshi Georgia Inst. of Technology USA
SupeRBNN Superconductor Accelerator Zhengang Li, OliviaChen Northeastern University, Tokyo City University USA,Japan
SUSHI Superconductor Chip Zeshi Liu, GuangMing Tang, Haihang You ICT China
Microarchitectures for Superconducting Quantum Samuel Stein, Michael DeMarco Pacific Northwest National Laboratory, MIT USA
Data Prefetching Biswabandan Panda Indian Institute of Technology Bombay India
MVC Processing in Memory Daichi Fujiki Keio University Japan
HARP Sparse Matrix MultiplicationAccelerator Jinkwon Kim, Soontae Kim KAIST koera
Victima AddressTranslation Konstantinos Kanellopoulos, Onur Mutlu ETH Zürich Switzerland
MetaVRain 3D-NeRF Processor Donghyeon Han, Hoi-Jun Yoo Korea Advanced Institute of Science and Technology Koera
1.28μm 50Mpixel CMOS Image Sensor Hyuncheol Kim, JoonSeo Yim Samsung Electronics Koera
Chip-to-Chip Interconnect Ying Wei, Edward Lee Nvidia USA
IPU Naru Sundar, Nupur Jain Intel USA
1mW Neural Decision Processor David Garrett, Atul Gupta Syntiant USA
28nm 16.9-300TOPS/W Computing-in-Memory Processor Jinshan Yue, Ming Liu Institute of Microelectronics of the Chinese Academy of Sciences China
12.4TOPS/W @ 136GOPS AI-IoT SoC Francesco Conti, Luca Benini University of Bologna, ETH Zürich Italy, Switzerland
Tesla ML Training Processor Tim C. Fischer, Te-Chen Tsai Tesla USA
ANP-I Edge-AI Processor Jilin Zhang, Hong Chen Tsinghua University China
ValueExpert GPU-accelerated
Keren Zhou, Xu Liu 		Rice University, North Carolina State University USA
Full-stack Accelerator Search Technique Dan Zhang, Azalia Mirhoseini Google USA
GPUReplay Heejin Park, Felix Xiaozhu Lin Purdue University, University of Virginia USA
FlexDriver network connecting Haggai Eran, Mark Silberstein NVIDIA, Technion Israel
Encrypted Data Using GPGPU Shengyu Fan, Rui Hou, Dan Meng, Mingzhe Zhang Institute of Information Engineering China
Wire-driven microarchitecture designs for cryogenic computing Dongmoon Min, Jangwoo Kim Seoul National University Koera
automated design space exploration Thilini Kaushalya Bandara, Li-Shiuan Peh National University of Singapore Singapore
Space-Efficient TREC Jiesong Liu, Xipeng Shen Renmin University of China, North Carolina State University China,USA
Neuromorphic hardware Ouwen Jin, Gang Pan Zhejiang University China
SIMD co-processor Zhongcheng Zhang, Yan Ou, Ying Liu ICT,HiSilicon Technologies Company, Zhongguancun Laboratory China
GPU Accelerated Zero-Knowledge Proof Weiliang Ma, Qian Xiong, Xuanhua Shi Huazhong University of Science and Technology China
Automatically Constrained High-Performance Library Generation Jun Bi, Qi Guo ICT China
logic Design Accelerating RTL Simulation Fares Elsabbagh, Daniel Sanchez MIT USA
Logic Synthesis Ceyu Xu, Lisa Wu Wills Duke USA
RTL Simulation Kexing Zhou, Ru Huang Peking University China
LEGO architecture Chong Zhang, Li Lu, Hongzi Zhu University of Electronic Science and Technology of China,Shanghai Jiao Tong University China
A Framework for Analyzing Quantum Circuit Siwei Tan, Jianwei Yin Zhejiang University China
Pysical Design 2D-FET device integration S. Kundu, G. S. Kar IMEC Belgium
Microcomb-driven silicon photonic systems Haowen Shu, Lin Chang, Yuansheng Tao, Bitao Shen, Xingjun Wang, John E. Bowers Peking University, UCSB China,USA
Verification and Simulation Quantum-Classical Interface Simulator Dongmoon Min, Jangwoo Kim Seoul National University Korea
Energy modeling for CMOS Image Sensors Tianrui Ma, Yu Feng,Xuan Zhang, Yuhao Zhu† Washington University, University of Rochester USA
Robotics SoC Simulator Dima Nikiforov，Yakun Sophia Shao UC Berkeley USA
Evaluation framework for CDPUs Sagar Karandikar, Parthasarathy Ranganathan UC Berkeley, Google USA
Photon GPU Simulation Changxi Liu, TrevorE. Carlson National University of Singapore Singapore
Manufacture Materials 2D Materials for Scaled Digital and Analog Devin Verreck, Gouri Sankar Kar IMEC Belgium
Indium-Tin-Oxide (ITO) 2T Gain Cell Kasidit Toprasertpong, H.-S. Philip Wong Stanford University, the University of Tokyo USA,Japan
2D Materials in the BEOL C. H. Naylor, M. Metz Intel USA
A Nanosheet Oxide Semiconductor FET Kaito Hikake, Masaharu Kobayashi The University of Tokyo Japan
Transistors In2O3 Radio-Frequency Transistors Dongqi Zheng, Peide D. Ye Purdue University USA
high-performance ITO TFTs Yuye Kang, Xiao Gong National University of Singapore Singapore
Vertical MoS2 transistor Fan Wu, He Tian, Yang Shen, Tian-Ling Ren Tsinghua University China
Optical ZyvexLitho1 Zyvex USA
Packaging Panel-Level Packaging John H. Lau, Tzyy-Jang Tseng Unimicron Technology Corporation China
Surface Mount Photonic Packaging Lars Brusberg, Robert A. Bellman Corning Research and Development Corporation USA
Fan-out Packaging Laurene Yip, Cooper Peng MediaTek Inc China
RDL-First Fan-Out Panel-Level Packaging
Chang-Chun Lee, Chin-Yi Chen 		National Tsing Hua University China
Product VisionFive 2 StarFive China
LeapFive NB2 LeapFive China
Wujian 600 Alibaba China
Apple M2 Apple USA
Intel Raptor Lake Intel USA
RTX40 Nvidia USA
CV3 Ambarella USA
BR100 BIRENTECH China
Kirin 9000S Huawei China
AMD Zen 4 AMD USA


Top Chips Contributors

Contributor Institution Country
Shurui Li UCLA USA
Puneet Gupta UCLA USA
Bokyung Kim Duke University USA
Hai Li Duke University USA
Yunjin Wang The Pennsylvania State University USA
Niranjan Soundararajan Intel Lab India
Haoran You Georgia Institute of Technology USA
Yingyan Lin Georgia Institute of Technology USA
Ang Li Princeton USA
David Wentzlaff Princeton USA
Hans Kasan KAIST Koera
John Kim KAIST Koera
Rishov Sarkar Georgia Institute of Technology USA
Cong Hao Georgia Institute of Technology USA
Xiaoyang Lu Illinois Institute of Technology USA
Xian-He Sun Illinois Institute of Technology USA
Julian Pavon Barcelona Supercomputing Center,Universitat Politecnica de Catalunya Spain
Adrian Cristal Barcelona Supercomputing Center,Universitat Politecnica de Catalunya Spain
Zichen Fan University of Michigan USA
Dennis Sylvester University of Michigan USA
Dibei Chen Tsinghua University China
Leibo Liu Tsinghua University China
Srivatsan Krishnan Harvard University USA
Vijay Janapa Reddi Harvard University USA
Gerasimos Gerogiannis UIUC USA
Josep Torrellas UIUC USA
Junseo Lee Seoul National University Korea
Jaewoong Sim Seoul National University Korea
Tanner Andrulis MIT USA
Vivienne Sze MIT USA
Xiaofeng Hou ACCESS, Shanghai Jiao Tong University China
Chao Li ACCESS, Shanghai Jiao Tong University China
Kwang-Ting Cheng ACCESS, Shanghai Jiao Tong University China
Norman P. Jouppi Google USA
David Patterson Google USA
Maolin Wang AI Chip Center for Emerging Smart Systems, University of Hong Kong China
Hayden Kwok-Hay So AI Chip Center for Emerging Smart Systems, University of Hong Kong China
Muhammad Husnain Mubarik UIUC USA
Rakesh Kumar UIUC USA
Siqi Li UCSB USA
Yuan Xie DAMO Academy China
Shiqing Zhang Ghent University Belgium
Lieven Eeckhout Ghent University Belgium
Junehyuk Boo Seoul National University, MangoBoost Inc Korea
Jangwoo Kim Seoul National University, MangoBoost Inc Korea
Dan Chen Huazhong University of Science and Technology China
Long Zheng Huazhong University of Science and Technology China
Nayana Prasad Nagendra Princeton University USA
Bhargav Reddy Godala Princeton University USA
David I. August Princeton University USA
Ajeya Naithani Ghent University Belgium
Faiz Alam North Carolina State University USA
Amro Awad North Carolina State University USA
Arthur Perais CNRS France
Rami Sheikh ARM UK
David Schall University of Edinburgh UK
Boris Grot University of Edinburgh UK
Chen Bai The Chinese University of HongKong China
Haoyang Zhang UIUC USA
Jian Huang UIUC USA
Suhas Vittal Georgia Inst. of Technology USA
Moinuddin Qureshi Georgia Inst. of Technology USA
Zhengang Li Northeastern University USA
OliviaChen Tokyo City University Japan
Zeshi Liu ICT China
GuangMing Tang ICT China
Haihang You ICT China
Samuel Stein Pacific Northwest National Laboratory USA
Michael DeMarco MIT USA
Ninghui Sun ICT China
Weiwu Hu Loongson,ICT China
Biswabandan Panda Indian Institute of Technology Bombay India
Daichi Fujiki Keio University Japan
Jinkwon Kim KAIST Korea
Soontae Kim KAIST Korea
Konstantinos Kanellopoulos ETH Zürich Switzerland
Onur Mutlu ETH Zürich Switzerland
Donghyeon Han Korea Advanced Institute of Science and Technology Koera
Hoi-Jun Yoo Korea Advanced Institute of Science and Technology Koera
Hyuncheol Kim Samsung Electronics Koera
JoonSeo Yim Samsung Electronics Koera
Ying Wei Nvidia USA
Edward Lee Nvidia USA
Naru Sundar Intel USA
Nupur Jain Intel USA
David Garrett Syntiant USA
Atul Gupta Syntiant USA
Jinshan Yue Institute of Microelectronics of the Chinese Academy of Sciences China
Ming Liu Institute of Microelectronics of the Chinese Academy of Sciences China
Francesco Conti University of Bologna Italy
Luca Benini ETH Zürich Switzerland
Tim C. Fischer Tesla USA
Te-Chen Tsai Tesla USA
Jilin Zhang Tsinghua University China
Hong Chen Tsinghua University China
Keren Zhou Rice University USA
Xu Liu North Carolina State University USA
Dan Zhang Google USA
Azalia Mirhoseini Google USA
Heejin Park Purdue University USA
Felix Xiaozhu Lin University of Virginia USA
Haggai Eran NVIDIA USA
Mark Silberstein Technion Israel
Shengyu Fan Institute of Information Engineering China
Rui Hou Institute of Information Engineering China
Dan Meng Institute of Information Engineering China
Mingzhe Zhang Institute of Information Engineering China
Dongmoon Min Seoul National University Koera
Thilini Kaushalya Bandara National University of Singapore Singapore
Li-Shiuan Peh National University of Singapore Singapore
Jiesong Liu Renmin University of China China
Xipeng Shen North Carolina State University USA
Ouwen Jin Zhejiang University China
Gang Pan Zhejiang University China
Zhongcheng Zhang ICT China
Yan Ou Huawei China
Ying Liu ICT China
Weiliang Ma Huazhong University of Science and Technology China
Qian Xiong Huazhong University of Science and Technology China
Xuanhua Shi Huazhong University of Science and Technology China
Jun Bi ICT China
Qi Guo ICT China
Fares Elsabbagh MIT USA
Daniel Sanchez MIT USA
Ceyu Xu Duke University USA
Lisa Wu Wills Duke University USA
Kexing Zhou Peking University China
Ru Huang Peking University China
Chong Zhang University of Electronic Science and Technology of China China
Li Lu University of Electronic Science and Technology of China, China
Hongzi Zhu Shanghai Jiao Tong University China
Siwei Tan Zhejiang University China
Jianwei Yin Zhejiang University China
S. Kundu IMEC Belgium
G. S. Kar IMEC Belgium
Haowen Shu Peking University China
Lin Chang Peking University China
Yuansheng Tao Peking University China
Bitao Shen Peking University China
Xingjun Wang Peking University China
John E. Bowers UCSB USA
Tianrui Ma Washington University USA
Yu Feng University of Rochester USA
Xuan Zhang Washington University USA
Yuhao Zhu University of Rochester USA
Dima Nikiforov UC Berkeley USA
Yakun Sophia Shao UC Berkeley USA
Sagar Karandikar UC Berkeley USA
Parthasarathy Ranganathan Google USA
Changxi Liu National University of Singapore Singapore
TrevorE. Carlson National University of Singapore Singapore
Jiangxing Wu NDSC China
Devin Verreck IMEC Belgium
Gouri Sankar Kar IMEC Belgium
Kasidit Toprasertpong Stanford University, The University of Tokyo USA
H.-S. Philip Wong Stanford University USA
C. H. Naylor Intel USA
M. Metz Intel USA
Kaito Hikake The University of Tokyo Japan
Masaharu Kobayashi The University of Tokyo Japan
Dongqi Zheng Purdue University USA
Peide D. Ye Purdue University USA
Yuye Kang National University of Singapore Singapore
Xiao Gong National University of Singapore Singapore
Fan Wu Tsinghua University China
He Tian Tsinghua University China
Yang Shen Tsinghua University China
Tian-Ling Ren Tsinghua University China
John H. Lau Unimicron Technology Corporation China
Tzyy-Jang Tseng Unimicron Technology Corporation China
Lars Brusberg Corning Research and Development Corporation USA
Robert A. Bellman Corning Research and Development Corporation USA
Laurene Yip MediaTek Inc China
Cooper Peng MediaTek Inc China
Chang-Chun Lee National Tsing Hua University China
Chin-Yi Chen National Tsing Hua University China
Lixin Zhang Sudo Information Technology China


Top Chips Institutions

Ranking Institute Grade Country
1 Intel 3.5 USA
1 Seoul National University 3.5 Korea
2 ICT,CAS 3.3 China
3 Georgia Institute of Technology 3 USA
3 Tsinghua University 3 China
3 UIUC 3 USA
3 KAIST 3 Korea
3 National University of Singapore 3 Singapore
4 MIT 2.5 USA
4 Nvidia 2.5 USA
4 Google 2.5 USA
5 Ghent University 2 Belgium
5 Huazhong University of Science and Technology 2 China
5 North Carolina State University 2 USA
5 Zhejiang University 2 China
5 IMEC 2 Belgium
5 Princeton 2 USA
5 Alibaba 2 China
5 Duke University 2 USA
6 ETH Zürich 1.5 Switzerland
6 Purdue University 1.5 USA
6 Peking University 1.5 China
6 The University of Tokyo 1.5 Japan
6 UC Berkeley 1.5 USA
7 Huawei 1.3 China
8 Princeton 1 USA
8 Illinois Institute of Technology 1 USA
8 Loongson 1 China
8 AMD 1 USA
8 University of Michigan 1 USA
8 Harvard University 1 USA
8 Shanghai Jiao Tong University 1 China
8 UCLA 1 USA
8 UCSB 1 USA
8 University of Edinburgh 1 UK
8 Indian Institute of Technology Bombay 1 India
8 Keio University 1 Japan
8 Samsung Electronics 1 Korea
8 Syntiant 1 USA
8 Institute of Microelectronics,CAS 1 China
8 Tesla 1 USA
8 Institute of Information Engineering,CAS 1 China
8 NDSC 1 China
8 Zyvex 1 USA
8 Unimicron Technology Corporation 1 China
8 Corning Research and Development Corporation 1 USA
8 MediaTek Inc 1 China
8 National Tsing Hua University 1 China
8 StarFive 1 China
8 LeapFive 1 China
8 Apple 1 USA
8 Ambarella 1 USA
8 ACCESS 1 China
8 BIRENTECH 1 China
9 The Pennsylvania State University 0.5 USA
9 Barcelona Supercomputing Center 0.5 Spain
9 Universitat Politecnica de Catalunya 0.5 Spain
9 University of Hong Kong 0.5 China
9 MangoBoost Inc 0.5 Korea
9 CNRS 0.5 France
9 ARM 0.5 UK
9 The Chinese University of HongKong 0.5 China
9 Northeastern University 0.5 USA
9 Tokyo City University 0.5 Japan
9 Pacific Northwest National Laboratory 0.5 USA
9 University of Bologna 0.5 Italy
9 Rice University 0.5 USA
9 University of Virginia 0.5 USA
9 Technion 0.5 Israel
9 Renmin University of China 0.5 China
9 University of Electronic Science and Technology of China 0.5 China
9 Washington University 0.5 USA
9 University of Rochester 0.5 USA
9 Stanford University 0.5 USA
10 Zhongguancun Laboratory 0.3 China


Top Chips Countries

Ranking Country Grade
1 USA 41
2 China 30.5
3 Korea 8
4 Belgium 4
5 Japan 3
5 Singapore 3
6 UK 1.5
6 India 1.5
6 Switzerland 1.5
7 Spain 1
8 France 0.5
8 Israel 0.5
8 Italy 0.5